Advanced Memory Optimization Techniques for Low-Power by Manish Verma, Peter Marwedel

By Manish Verma, Peter Marwedel

The layout of embedded platforms warrants a brand new standpoint as a result following purposes: to begin with, gradual and effort inefficient reminiscence hierarchies have already turn into the bottleneck of the embedded platforms. it's documented within the literature because the reminiscence wall challenge. Secondly, the software program operating at the modern embedded units is changing into more and more complicated. it's also good understood that no silver bullet exists to unravel the reminiscence wall challenge. consequently, this booklet explores a collaborative procedure via offering novel reminiscence hierarchies and software program optimization suggestions for the optimum usage of those reminiscence hierarchies. Linking reminiscence structure layout with memory-architecture acutely aware compilation leads to speedy, energy-efficient and timing predictable reminiscence accesses. The review of the optimization recommendations utilizing real-life benchmarks for a unmarried processor approach, a multiprocessor system-on-chip (SoC) and for a electronic sign processor process, reviews major rate reductions within the power intake and function development of those platforms. The e-book offers quite a lot of optimizations, steadily expanding within the complexity of research and of reminiscence hierarchies. the ultimate bankruptcy covers optimization ideas for functions together with a number of strategies present in most recent embedded units. complicated reminiscence Optimization suggestions for Low energy Embedded Processors is designed for researchers, complier writers and embedded process designers / architects who desire to optimize the power and function features of the reminiscence subsystem.

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C) FIR Fig. 9. Normalized Energy Comparison of Scratchpad Allocation Approaches and therefore, the larger is the reduction in the total energy consumption of the system. The SA approach achieves a maximum total energy reduction of 71%, 84%, 87% and 88% for main memories with 1, 5, 10 and 20 master clock latencies, respectively. 3 M5 DSP The M5 DSP in its default configuration contains a large onchip group memory to hold the data variables. The energy dissipation of the data memory hierarchy is improved by inserting a small and energy efficient L1 scratchpad or group memory.

An accurate memory energy model from UMC is used to compute the energy consumption of the data memory subsystem. However, due to copyright reasons, we are forbidden to report exact energy values. Therefore, only normalized energy values for the data memory subsystem of the M5 DSP will be reported in this work. The compilation framework for the M5 DSP is similar to that for the uni-processor ARM based system. The only significant difference between the two is that the compiler for the M5 DSP uses a phase coupled code generator [80].

Several test programs which utilized the scratchpad memory were executed and their energy consumption was computed. This energy data along with the linear equation of the energy model (cf. 2) was used to derive the energy per access values for the scratchpad memory. Fig. 4. 2 Compilation Framework The compilation framework for a uni-processor ARM is based on the energy optimizing C compiler ENCC [37]. 4, ENCC takes application source code written in ANSI C [7] as input and generates an optimized assembly file containing Thumb mode instructions.

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